Design of AI firmware for a 2-core big-little RISC-V SoC with 2 NPUs

Introduction

Synthara’s new System on Chip (SoC) leverages a 2-core big-little RISC-V architecture and includes two AI accelerators, Nullhop and Watchdog, also operating in a big-little configuration. This innovative SoC stands as a pivotal advancement for AI and neural network processing, aiming to deliver high efficiency and flexibility. This project focuses on the development of firmware and software to enable neural network operations on this SoC, capitalizing on the unique architecture to optimize performance.

Project Proposal

The proposed project is centered on the design and implementation of firmware and software for running neural networks on the new SoC. This involves leveraging the RISC-V cores and AI accelerators to enhance processing capabilities and efficiency.

The main objectives of the project are:

  • Understand the Architecture and Functionality:
    • Gain a comprehensive understanding of the 2-core big-little RISC-V SoC and its integration with the Nullhop and Watchdog AI accelerators.
    • Analyze the big-little configuration and its implications for performance and efficiency.
  • Design and Implement Firmware:
    • Develop firmware to manage the SoC’s resources effectively, ensuring optimal coordination between the RISC-V cores and AI accelerators.
    • Implement low-level software components that facilitate efficient communication and data transfer within the SoC.
  • Neural Network Integration:
    • Adapt existing neural network frameworks to leverage the capabilities of the SoC.
    • Implement and optimize neural network operations, ensuring they can effectively utilize both the RISC-V cores and AI accelerators.
  • Documentation and Collaboration:
    • Provide comprehensive documentation detailing the design, implementation, testing, and potential applications of the firmware and software.
    • Collaborate closely with Synthara’s team to integrate the developed solutions into the existing ecosystem and contribute to future advancements.

We are looking for individuals who are strong in at least one of the areas outlined in the project and are enthusiastic about learning and contributing to other areas.  The position is open to students or newly graduates with different backgrounds, from software/programming to engineering/FPGA, as we are building a small team to collaborate on the task.

Intern Profile

  • Academic background: computer science, electronic engineering, AI, or related fields with an emphasis on neural networks and in-memory computing.
  • Coding languages: Python, C/C++ for SW work, SystemVerilog (preferred, VHDL also ok) for FPGA work.
  • Duration: 6 to 9 months, flexible as per the academic requirement.

    Your CV