Verification – Design of a UVM-based RISC-V model for Digital Functional Verification

Introduction

Synthara AG is at the forefront of AI innovation, focusing on creating low-power solutions for advanced applications. As part of our ongoing commitment to cutting-edge technology, we are proud to collaborate with the OpenHW group under the European grant TRISTAN project.
This proposal aims to develop and verify a customizable and extendable SystemVerilog model of a RISC-V processor.
We are seeking a talented and motivated intern to contribute to the digital verification of this core, addressing critical challenges such as interrupt handling and model integration within an RTL simulator environment.

Project Proposal

The primary objective of this internship is to support the development and verification of a RISC-V processor model. The intern will be involved in the following key activities:

  • Design a customizable and extendable SystemVerilog UVM-based model of a RISC-V processor.
  • Ensure the model can support the verification of CV32E20.
  • Ensure the model can support custom ISA instructions.
  • Identify and overcome challenges associated with interrupt handling within the RISC-V core.
  • Integrate the developed SystemVerilog model into an RTL simulator environment.
  • Conduct comprehensive testing and validation to ensure seamless operation within the simulation framework.

Intern Profile

  • Academic background: electronic engineering, computer science, AI, or mathematics or related fields.
  • Coding languages: Familiarity with programming languages like C and C++, Python. Knowledge and experience with RISC-V processor architecture and  SystemVerilog/UVM is preferable. 
  • Duration: 8 to 12 months, flexible as per the academic requirement

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