Open Positions

Join Synthara's software team and own the virtual platforms for ComputeRAM®. These platforms serve as reference systems for pre-silicon software prototyping and HW/SW co-verification. They must be accurate, usable, and continuously validated. You sit between hardware and software. Your job is to make both sides work together and expose issues early.

Join Synthara’s applications team and help demonstrate and deploy ComputeRAM®s on customer systems and AI, signal-processing and cryptography workloads. You will work at the intersection of machine learning, signal-processing, embedded systems, computer architecture, compilers, simulators and customer applications. You will analyse and implement representative workloads, map their computational operations onto ComputeRAM, benchmark their performance and energy efficiency, and use those results to guide both customer engagements and product development. You will also work closely with Synthara’s customers, supporting them in adding ComputeRAM® to their existing products. This is a hands-on, cross-functional role. You will work with ML and AI models, as well as signal-processing and cryptography algorithms at the application level, but also reason about hardware constraints and tradeoffs, memory movement, numerical precision, system architecture, and performance. You will collaborate closely with software, applications, platform and hardware engineers, management and sales representatives, while also supporting customer-facing proofs-of-concept, workshops, pre-sales and technical discussions.

Own timing closure and sign-off for complex IP and SoC blocks that integrate our full-custom ComputeRAM® macros. You will drive Static Timing Analysis across corners and modes, shape clean constraints, partner closely with synthesis, place-and-route, and clock-tree teams, and lead ECO loops to convergence. Your work ensures robust clocks, predictable closure, and high-quality sign-off on modern nodes. You will work closely with our full-custom team to integrate our custom IPs into the traditional digital backend flow.

Own the end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems and build the backend team that scales it. You’ll define the methodology, constraints, and quality metrics that the team shall adhere to. The team you lead will be responsible for synthesis, floor planning, P&R, clock tree synthesis, multi-corner STA, design for testability, and ECOs to achieve sign-off. You and your team will collaborate tightly not only with our RTL/digital team but also with our full-custom and full-custom layout team, integrating our full-custom design blocks into a digital-on-top mixed ASIC design. This is a hands-on technical leadership role, where you will not only set the flow and lead the team, but also personally de-risk and own the most challenging aspects of the design.

Own critical mixed-signal subsystems that bring our compute-in-memory SRAM (ComputeRAM®) from design to silicon and into production. You will design, verify, and characterize custom blocks, including full-custom digital datapaths and memories, and collaborate tightly with our digital and layout teams to hit aggressive PPA and quality targets on modern CMOS nodes, down to 4nm and below. You will deal with multi-disciplinary topics ranging from traditional mixed-signal design to solving digital timing constraints.

Design and ship high-performance, low-power SRAM and custom-digital sub-systems that sit at the core of our compute-in-memory technology. You will own architecture, circuit implementation, verification, and silicon correlation for advanced nodes, down to sub-5 nm, thereby improving both the efficiency and robustness of our macros. Expect hands-on work on memory periphery and datapath interfaces, as well as close collaboration with layout, digital, backend, DFT, and test teams.

Lead the development of high-performance, custom based digital compute or SRAM memory designs to power our compute-in-memory SRAM (ComputeRAM®). You will own architecture, circuit design, verification, and silicon correlation for advanced nodes down to 5 nm and below, and you will lead a small team of custom designers and layout engineers to predictable, production-grade outcomes. Expect hands-on work on bitcell-adjacent periphery, datapath interfaces, optimizing data movement, as well as tight collaboration with full-custom layout, digital, backend, DFT, and test.

Join the core software team that turns ComputeRAM® into something developers love to use. You will design and ship a software integration kit, build the software library components that sit between applications and hardware, develop compiler passes that lower NN/DSP ops to our primitives, and own a solid benchmarking pipeline. You will work closely with silicon and equally closely with users, moving from prototype to production with clean code, clear documentation, and measurable speed and energy gains.

Own the design and verification of part of our digital IP portfolio that wraps and integrates our compute-in-memory technology(ComputeRAM®): clean, synthesis-ready SystemVerilog RTL, plus UVM environments that reach coverage closure and de-risk silicon. You’ll specify and build register/bus interfaces, DMA, and control logic. Expect tight collaboration with custom design, backend, and software teams to hit PPA, coverage, and time-to-tapeout simultaneously.

Own transistor-level and block-level custom layout for mixed-signal, SRAM, and custom-digital IP that powers our compute-in-memory SRAM (ComputeRAM®). You will plan floorplans, implement device-level layouts with production-grade matching/guarding, close DRC/LVS/PEX on advanced nodes down to 4 nm and below, and collaborate tightly with custom-design, digital, and PD/STA teams to hit aggressive PPA, yield, and reliability targets. You will bridge classic analog techniques (common-centroid/interdigitation, shielding, isolation) with FinFET/FDSOI rules, multi-patterning/EUV constraints, and modern DFM practices.